ASIC Manager

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Experience: 9+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experienced Senior Verification Lead to lead the verification of high-speed IPs and subsystems, with a strong focus on PCIe, SystemVerilog, UVM, and SoC verification methodologies.

The role combines deep technical expertise, verification strategy, team leadership, automation, and cross-functional collaboration. You will be responsible for driving high-quality IP and subsystem verification, establishing scalable methodologies, supporting silicon bring-up, and enabling multiple verification programs to execute efficiently and reliably.

Key Responsibilities

• Lead verification of high-speed IPs and subsystems, including PCIe-based designs, using SystemVerilog and UVM.
• Define verification strategies, methodologies, plans, schedules, milestones, and deliverables for IP and subsystem programs.
• Drive end-to-end verification execution from specification analysis through product qualification and silicon bring-up.
• Establish scalable, reusable, portable, and efficient verification environments and methodologies.
• Develop and implement automation solutions to improve verification productivity, coverage, quality, and execution efficiency.
• Collaborate closely with Architecture and Design teams to understand requirements and align verification flows and deliverables.
• Review architecture and design specifications and translate requirements into comprehensive verification strategies.
• Lead verification closure, including coverage analysis, regression management, defect tracking, and quality assessment.
• Drive verification of PCIe Root Complex, Endpoint, and SR-IOV functionality.
• Support verification involving industry-standard interfaces and architectures such as PCIe/NVMe, NAND, and AXI.
• Lead and support silicon bring-up activities and collaborate with hardware and engineering teams to resolve silicon-level issues.
• Plan team capacity and ramp-up to support verification of multiple IPs and subsystems in parallel.
• Manage technical execution across challenging schedules while maintaining verification quality and delivery commitments.
• Establish best practices for verification automation, portability, reusability, and continuous improvement.
• Collaborate with engineering teams across multiple geographies to coordinate execution and resolve dependencies.
• Provide technical mentoring, coaching, and career development support to verification engineers and technical leads.
• Identify verification risks, execution bottlenecks, and methodology gaps and drive appropriate corrective actions.
• Contribute to continuous improvement of verification processes, tools, frameworks, and engineering practices.

What Makes You a Great Fit

• 14+ years of overall verification experience, with strong expertise in semiconductor IP, subsystem, and SoC verification.
• 12+ years of hands-on experience in IP/subsystem verification using SystemVerilog and UVM.
• Expert-level knowledge of PCIe protocols, including Root Complex, Endpoint, and SR-IOV functionality.
• Strong understanding of SoC verification methodologies, processor architectures, and storage controller architectures.
• Experience with industry-standard interfaces such as PCIe/NVMe, NAND, and AXI is highly desirable.
• Proven experience leading and managing teams of 10+ engineers and technical leads.
• Strong experience defining verification strategies, methodologies, environments, coverage plans, and execution frameworks.
• Demonstrated ability to drive automation, portability, reusability, and verification efficiency.
• Experience leading complex verification programs through challenging schedules and multiple parallel deliverables.
• Hands-on experience with silicon bring-up and post-silicon debugging.
• Strong collaboration skills with Architecture, Design, Validation, Firmware, and other engineering teams across multiple geographies.
• Excellent technical leadership, mentoring, coaching, and people-management capabilities.
• Strong analytical and problem-solving skills with the ability to identify risks and drive issues to closure.
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.