Design Engineer II - Digital Design

Job Title: ASIC Front -End Design Engineer

Skills & Experience:

• 2–5 years of experience in ASIC Front -End Design and Quality Checks
  
• Strong fundamentals in Digital Design and Verilog
  
• Experience working with multiple clock and voltage domains
  
• Hands -on knowledge of front -end flows: Lint, CDC, Synthesis, and related quality checks
  
• Familiarity with scripting languages
  
• Understanding of UPF and low -power checks (preferred)
  
• Exposure to memory controller / cache / memory subsystem is an added advantage
  
• Good communication skills; experience working with global teams is desirable
  

Key Responsibilities:

• Perform RTL front -end quality checks (Lint, CDC, Synthesis, LEC, Low Power)
  
• Develop and debug constraints for QA flows
  
• Work closely with SoC/subsystem integration teams on design integration and debugging
  
• Collaborate with cross -functional teams to ensure smooth and timely execution
  
• Support activities across synthesis, DFT, integration, and post -silicon debug
  
• Coordinate with global teams across different time zones