Field Application Engineer IC Design & Verification - Bengaluru

The Role

As a Field Application Engineer — IC Design & Verification, you will be the technical expert for GSAS's semiconductor EDA portfolio — covering IC physical verification and signoff, silicon test and yield optimization, and variation -aware custom IC design. You'll work with semiconductor design houses, foundry interface teams, DFT engineers, analog/mixed -signal designers, and verification leads across India's growing chip design ecosystem to help them evaluate, adopt, and maximize the value of world -class IC tools.

This role lives in the semiconductor world, not the board world. Your customers are designing silicon — digital SoCs, analog/mixed -signal ICs, automotive -grade chips, RF front -ends, and custom ASICs. You need to understand what happens between RTL and GDSII, how test gets inserted into a design, how variation affects analog circuit performance, and what a foundry expects in a signoff -clean tapeout package. If you've worked in a semiconductor design flow and want to bring that experience to a customer -facing role, this is it.

Key Responsibilities

Deliver technical demonstrations, evaluations, benchmarks, and proof -of -concept engagements for GSAS's IC EDA portfolio — spanning physical verification and DFM optimization (DRC, LVS, parasitic extraction, pattern matching, OPC/RET), silicon test and lifecycle management (DFT insertion, ATPG, BIST, scan compression, in -system test, yield analysis, safety mechanisms), and variation -aware custom IC design (SPICE simulation, Monte Carlo analysis, library characterization, IP validation).

Support physical verification workflows for tapeout readiness — DRC rule deck setup and debug, LVS matching and error resolution, parasitic extraction (PEX) for timing and signal integrity closure, fill insertion, antenna check, and foundry -specific DFM checks. Help customers integrate physical verification into their signoff flow and reduce iteration cycles between design and foundry.

Guide DFT and test engineering teams through silicon test tool adoption — scan chain insertion, ATPG pattern generation, test compression configuration, BIST implementation (logic and memory), fault coverage analysis, yield analysis and diagnosis, and in -system test for automotive safety applications (ISO 26262 hardware fault metrics). Support customers in building test flows that balance coverage, pattern count, and test time.

Support analog and mixed -signal design teams with variation -aware design and verification workflows — process corner analysis, Monte Carlo simulation, statistical design, library characterization for standard cells and I/O libraries, and IP validation. Help customers understand how variation affects circuit performance and how ML -powered analysis tools can reduce simulation time while improving coverage.

Provide pre -sales and post -sales technical support: tool installation, PDK and technology file configuration, license setup, flow integration with third -party tools (synthesis, place -and -route, timing signoff), and hands -on training for design teams. Support migration from competing platforms and help customers establish or optimize their verification and test methodologies.

Work with foundry interface teams to ensure design kits, rule decks, and technology files are properly configured for the verification and signoff tools. Understand foundry -specific requirements and help customers navigate the tapeout checklist.

Collaborate with the sales team on opportunity qualification, technical proposal development, competitive positioning against Synopsys and Cadence tools, and RFP responses. Provide field intelligence on the Indian semiconductor design ecosystem — which design houses are growing, what process nodes they're targeting, which foundries they're using, and what tool gaps exist.

Stay current with semiconductor technology trends — advanced node challenges (FinFET, GAA), 2.5D/3D IC integration and chiplet -based design, automotive IC safety requirements, increasing DFT complexity for AI/ML chips, and the impact of India's semiconductor manufacturing initiatives on the domestic EDA market.

Contribute to GSAS's technical knowledge base: application notes on verification methodology, DFT best practices, variation -aware design workflows, competitive comparison documents, and workshop curricula for semiconductor design teams.

Requirements

3–6 years of hands -on experience in semiconductor IC design, DFT engineering, physical verification, or EDA application engineering in the IC domain. You've worked inside a chip design flow — not just at the board level. You understand what a tapeout involves, what DRC/LVS clean means, and why test coverage matters.

Deep experience in at least one of the following three domains, and working familiarity with at least one other:

Physical verification — DRC, LVS, parasitic extraction, antenna checks, DFM, fill, and the relationship between design rules and manufacturing process capabilities. Experience setting up or debugging rule decks and resolving LVS mismatches. Understanding of foundry signoff requirements at established nodes (28nm, 16nm, 7nm, or advanced).

Silicon test and DFT — scan insertion, ATPG, test compression, BIST (logic and memory), fault simulation, yield analysis, and diagnosis. Understanding of test cost tradeoffs — coverage vs. pattern count vs. test time. Exposure to automotive safety test requirements (ISO 26262 hardware metrics, in -system test) is a strong advantage.

Custom IC and analog/mixed -signal — SPICE simulation, corner and Monte Carlo analysis, variation -aware design methodology, library characterization (timing, power, noise), IP validation. Understanding of how process variation impacts analog circuit performance and how statistical methods improve design robustness.

Familiarity with semiconductor design flows and tool ecosystems — you understand where verification, test, and characterization fit in the RTL -to -GDSII and analog design flows, how they interact with synthesis, place -and -route, timing signoff, and foundry handoff. Experience with PDKs and foundry -specific design kits.

Understanding of the Indian semiconductor ecosystem — awareness of the major design houses, captive design centers, fabless startups, and government semiconductor initiatives. Knowledge of which process nodes and foundries are most active in India.

Strong communication and customer engagement skills. You can debug an LVS error with a layout engineer, present a DFT methodology to a verification lead, discuss fault coverage tradeoffs with a test engineering manager, and articulate tool value to a design director. Willingness to travel for customer engagements, training, and industry events.

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI Design, or a related discipline. Postgraduate specialization in VLSI, semiconductor devices, or IC design is preferred.

Benefits