High-Speed I/O Protocol Verification Lead

About the company:

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.

Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.

Anthriq Silicon is our ground-up effort to build a new compute category.

About the Role:
We're hiring a protocol verification authority to own sign-off on high-speed I/O interfaces for a next-gen SoC — PCIe Gen5, 32G+ SerDes, LPDDR5X, and Ethernet 25G-KR. This is an audit/authority role: you'll validate compliance logs, link-training, and PHY behavior delivered by our silicon partner before it clears sign-off.

Key responsibilities

• Audit and sign off PCIe Gen5 LTSSM logs, PIPE-interface timing, route/test cases.


• Validate LPDDR5X PHY initialization, training algorithms, PHY-to-controller handshakes.


• Audit 32G+ SerDes equalization, framing FSMs, lane-reversal/polarity, and JESD204B/C deterministic-latency alignment.


• Audit Ethernet 25G-KR MAC/PCS.


• Configure, run, and debug commercial VIP for high-speed protocols.

Must-have skills

• 8+ years in high-speed I/O protocol verification (PCIe Gen4/Gen5, LPDDR4/5X, 28G/32G/56G SerDes).


• JESD204B/C converter-interface verification with deterministic latency.


• Ethernet MAC/PCS (25G-KR / backplane).


• Commercial VIP integration and debug; strong protocol waveform analysis.

Nice-to-have

• TSMC 7nm/5nm PHY integration tuning.


• Performance benchmarking under I/O congestion.


• Target EDA tools: Cadence VIPs (PCIe, LPDDR, SerDes, JESD, Ethernet), Xcelium, Indago