Lead Engineer - DFT

We are hiring an experienced DFT (Design -for -Test) Lead to join our growing team. The ideal candidate will have strong technical expertise in Scan, ATPG, MBIST, post -silicon bring -up, and GLS (Timing Sim), along with proven leadership experience. If you're passionate about silicon quality and test architecture, this is your opportunity to shape high -impact silicon solutions from design to production.

Key Responsibilities:

• Lead and drive DFT architecture and implementation for SoCs.
  
• Hands -on execution of Scan/MBIST insertion, ATPG pattern generation & verification, MBIST verification, and GLS (Gate Level Simulation).
  
• Post -silicon bring -up support, debug, and yield analysis.
  
• Define and manage test mode timing constraints, work with timing teams for timing closure.
  
• Coordinate tapeout readiness from DFT standpoint and ensure test quality.
  
• Collaborate cross -functionally with RTL, STA, and PD teams for smooth integration.
  
• Mentor and guide junior engineers in DFT methodologies and best practices.
  
• Utilize scripting languages (Perl, Shell, etc.) for automation and flow enhancements.
  

Requirements