Senior Engineer - Frontend CAD

Join our Team

About this opportunity:

Are you a hands-on engineer and ready to shape the future of silicon verification methodology and tools on a global scale? 

Join our Design Verification Methodology team — a newly established global group defining methodologies and EDA workflows across our R&D sites in Bangalore, Austin, Stockholm, and Lund. 

We are part of the Ericsson Silicon engineering unit, developing state-of-the-art ASICs and FPGAs at advanced technology nodes for Ericsson’s 5G and 6G product portfolio. Our environment offers deep technical challenges, opportunities for growth, and a wealth of expertise to learn from. Last year we started a new Silicon R&D center in Bangalore, ready to join? 

You will do:

You will bring:

• Deep expertise in Testbench Architecture using SystemVerilog and UVM at IP, ASIC, and/or SoC level.


• Previous hands-on experience in scripting (Python, Perl, bash, csh, etc.).


• Strong knowledge of layered UVM environments, reusable testbench components, and block/subsystem/SoC-level verification strategies.


• Solid understanding of directed and constrained-random verification, SVA, functional and code coverage closure.


• Proficiency with front-end EDA tools: Verilog simulators, RTL/verification linters, CDC checkers, and formal verification.


• Experience with CI methodologies and tools (e.g., Jenkins).


• Strong grasp of modern silicon design methodologies and verification best practices.


• Experience collaborating across geographically distributed teams.


• Excellent communication skills and a strong sense of ownership in solving complex infrastructure challenges.


• Exposure to AI/ML applications in design and verification flows (e.g., testbench optimization, anomaly detection, coverage prediction) is a significant advantage. 

Responsibilities:

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“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”