Senior Lead Engineer Memory design

Summary: we are looking for a Lead memory design Engineer to join our NXP’s NVM IP design group in Bangalore, India. who can manage efficiently a multi-technology NVM IP portfolio, ensure the highest level of quality, and develop automated IP management solutions and team up with 3rd-party NVM IP vendors and NXP product design teams, to enable the high-quality and scalable NVM IP solutions across all NXP’s vertical markets.

Job Qualification:

• BS or MS in Electrical Engineering with +7 years of experience in either Analog design/ Memory design (SRAM/NVM) / IO design/ standard cell circuit design.
• Hands-on experience in scripting and flow automation
• Hands-on experience or sound knowledge of quality managed design flows, tools and methodologies (Cadence and Synopsys)
• Knowledge of NVM technology, macro architecture and design would be a significant advantage
• Excellent communication skills with proven experience in cross country team collaboration.

Job responsibilities:

As the Senior NVM IP Lead Engineer for our newly formed Bangalore team, you will be part of a Global NVM design department.  You will be leading the NVM IP benchmarking, onboarding, release and support competence for a wide 3rd-party NVM and NXP-proprietary IP platform including Logic-NVM, Flash, RRAM and MRAM. Your responsibilities will encompass:

• NVM IP benchmarking for a given product-technology requirements
• Execute IP onboarding (IP design kit preparation and verification) and release to SoC design team
• Support design SoC teams with NVM IP integration and troubleshooting
• Develop an automated IP onboarding and release flow to ensure flawless and efficient execution
• Maintain 3rd-party NVM and NXP-proprietary NVM IP portfolio spanning across the whole technology spectrum of the company from 180nm to 5nm
• Interact directly with 3rd-party vendors and silicon foundries
• Team up with NXP NVM design team in Bangalore, EU and US
• Mentor junior engineers growing in the NVM field

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