Senior/Principal Analog Layout Engineer

The Senior Analog Layout Engineer will be responsible for creating high‑performance IC layouts for complex analog, mixed‑signal, and custom circuits at both block and chip levels. This role requires a strong understanding of deep‑submicron CMOS processes, advanced layout techniques, and industry‑standard EDA tools. The ideal candidate will work closely with circuit designers to translate schematic requirements into robust, silicon‑proven physical layouts.

Primary Responsibilities:

• Perform full‑custom layout of analog and mixed‑signal building blocks, including amplifiers, ADC/DAC components, regulators, PLLs, bias circuits, sensors, and high‑precision analog modules.


• Execute top‑level floorplanning and routing strategies with careful consideration of performance, area optimization, power distribution, and signal integrity.


• Apply advanced matching techniques for transistors, resistors, and capacitors, ensuring low noise, high linearity, and optimal device performance in deep‑submicron technologies.


• Verify and debug physical layouts by resolving LVS, DRC, ERC, Antenna, and EM/IR reliability issues.


• Collaborate closely with circuit designers to understand layout‑dependent effects (LDE), performance trade‑offs, and design constraints.


• Ensure compliance with foundry technology rules and design guidelines while optimizing for manufacturability and yield (DFM).


• Generate and maintain documentation related to layout methodologies, constraints, and verification results.

Position Requirements:

• B.S. in Electrical Engineering (M.S./Ph.D. preferred)


• Hands‑on experience with industry‑standard CAD/EDA tools including Cadence Virtuoso, VXL, Assura, PVS, Calibre, and related verification tools.


• Strong understanding of parasitic extraction (PEX) and its impact on analog circuit performance.


• Proven ability to plan and execute block‑level and chip‑level layouts in advanced CMOS nodes.


• Solid knowledge of device matching, symmetry, common‑centroid layout, guard rings, shielding, dummy structures, and routing best practices.


• Ability to independently resolve verification errors and deliver clean, tape‑out‑ready layouts.


• Excellent written and verbal communication skills, with the ability to work effectively in a cross‑functional engineering team.


• Detail‑oriented, highly organized, and able to manage multiple tasks and deadlines.

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Forza Silicon designs custom and off‑the‑shelf CMOS image sensors for high‑speed, low‑noise, and specialty applications across aerospace, defense, medical, industrial, scientific and media markets. Leveraging decades of experience, we deliver advanced imaging solutions enabling customers to push beyond conventional sensor performance.  Forza has grown to where today the company employs one of the industry’s largest and most experienced independent CMOS imaging engineering teams.  To learn more about Forza Silicon, please go to www.forzasilicon.com.