Staff Digital Design Engineer

Overview

onsemi is seeking an experienced Staff Digital Design Engineer to join our Core Platform IP organization in Cork, Ireland. This role focuses on the development of digital controllers and digital-on-top subsystems for the onsemi Treo™ platform, enabling next-generation mixed-signal and power management solutions.

The successful candidate will play a key technical role at the intersection of digital logic, analog control, and system-level IP, working closely with analog, verification, and back-end teams. This is an opportunity to influence platform-level IP and contribute to innovative solutions that scale across multiple products.

Key Responsibilities

• Architect, design, and implement digital FSM-based controllers that manage and interact with analog power, clocking, and mixed-signal blocks


• Deliver robust digital-on-top subsystem IP in support of the onsemi Treo™ platform


• Develop clean, maintainable RTL (SystemVerilog / Verilog) suitable for reuse and scalability


• Collaborate closely with: 
  
  
  
  • Analog and mixed-signal designers to define control interfaces and behavior
  
  
  • Verification engineers to ensure functional correctness
  
  
  • Physical design teams to support timing, power, and area goals
  
  


• Contribute to digital verification activities, including: 
  
  
  
  • Testbench development
  
  
  • Block-level and subsystem-level verification
  
  
  • Debug and root-cause analysis
  
  


• Support digital back-end flows, including synthesis, timing closure, and low-power considerations


• Mentor junior engineers and contribute to best practices within the Core Platform IP team


• Stay technically curious and engaged, particularly around emerging AI-assisted methodologies for digital design and verification

Required Qualifications

• 5+ years of relevant experience in digital IC design


• Strong hands-on experience with digital RTL design, including FSM-based control logic


• Proven experience designing digital logic that interfaces with analog power and clocking systems


• Solid understanding of digital design fundamentals: 
  
  
  
  • Clock-domain crossing (CDC)
  
  
  • Reset strategies
  
  
  • Low-power techniques
  
  
  • Timing constraints
  
  


• Experience with digital verification, including simulation-based verification


• Exposure to digital back-end flows, such as synthesis, STA, and handoff to physical design


• Strong problem-solving skills and a system-level mindset


• Excellent communication skills and ability to work in a cross-functional environment

Preferred / Nice-to-Have Qualifications

• Experience delivering reusable IP or platform-level subsystems


• Familiarity with UVM-based verification environments


• Experience in mixed-signal or power management ICs


• Knowledge of low-power standards (e.g., UPF/CPF)


• Interest in or early adoption of AI/ML tools applied to digital design, verification, or productivity workflows