Design Verification Engineer

• Develop testbench components such as test, sequence libraries, bfm and monitor by using
  object oriented programming verification techniques following UVM methodology
  
  
• Automate validation environment to improve activities such as test writing, regression
  running or coverage collection
  
  
• Define detailed test plan from specification by working with architects and design engineers
  
  
• Write and debug tests in UVM/C++
  
  
• Incorporate function/code -coverage, assertions, cover -groups etc to achieve 100% verification
  completeness prior to tapeout
  

Requirements

• Knowledge in C, Python, shell scripting
  
  
• OVM/UVMvalidation methodology
  
  
• Verilog/System Verilog
  
  
• Great interpersonal and communication skills
  
  
• Teamplayer, critical thinker and problem solving skills