Senior IP Design Engineer

We are searching for our client, a global IT company, a Senior IP Design Engineer to join their business in Romania

Scope

• Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
  

Required Skills 

• SystemVerilog RTL design 
  

• 100Gb Ethernet, PCIe Gen5, AMBA/AXI 
  

• Deep understanding of FPGA/Adaptive SoC design flow including P& R and timing closure 
  

• Vivado/Vitis expertise 
  

• Python/Tcl scripting 
  

• Git & CI/CD experience 
  

If you know of anyone within your network who may also be interested in this position,would you please forward this ‘Email & Role’ to them.

Please note:

1. That we do all we can to respond to all applications but if we have not contacted you within 2 days following your application - its likely we have not shortlisted your CV for the position.
   

2. Manning Global cannot consider your application for this role if you are working for the customer we are recruiting for
   

3. If you are working for the client we are representing, but have confirmation you are leaving a permanent or contract position, please discuss this with us, so we can discuss representation with you.
   

4. This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the originator of the message. Any views expressed in this message are those of the individual sender.
   

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