Senior/Principal Researcher: Verified Agentic Hardware Optimization

Our company

Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

Our Research Center

With 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes our Research Center in Zurich, Switzerland. A major element of it is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, new algorithms).

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe and beyond. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such world-leading scientific work.

The project

Today, the intent behind a chip lives mostly in people’s heads. Constraints are inherited without rationale, encodings are chosen by habit, and the reasons behind design decisions are lost at commit time. Which properties of a design are essential and which could be changed is written down nowhere.

This is a fundamental obstacle for agentic hardware development. LLM-based agents now write syntactically correct RTL with ease, but without a machine-readable record of intent and freedom they cannot tell a legitimate optimization from a bug, and without automatic, trustworthy correctness checks their changes cannot be accepted at scale. Today’s verification flows make this harder still: the sequential transformations most worth exploring, such as retiming, re-pipelining and state re-encoding, are exactly the ones that are hardest to verify. As a result, a large reservoir of power, performance and area (PPA) stays locked away, out of reach for humans for lack of time and for agents for lack of trust.

For our Computing Systems Laboratory in Zürich, we are looking for an outstanding researcher at postdoc, senior or principal level to tackle these challenges. You will work in a small, motivated and multicultural team, in close collaboration with leading academic groups and with Huawei’s hardware design teams, and you will take a leading role in one or more of the research threads below. The level of the position will be matched to your experience.

Your responsibilities

• Design the specification and contract layer: an annotation language that gives each kind of relaxation a defined semantics, generates its own proof obligation, and composes with the others, on top of SystemVerilog and machine-readable normative specifications.

• Build the correctness gates: combinational and sequential equivalence checking, equivalence modulo a declared relaxation, model checking and reference-model-based differential testing, with a clear record of what each check established and what it did not.

• Extend agentic optimization loops in which LLM-based agents enumerate declared freedom, propose RTL edits, receive structured feedback with PPA estimates, and commit only what has been proven correct.

• Develop multi-fidelity PPA evaluation, from fast logic-level proxies to full synthesis and place-and-route, and study how agents should spend an evaluation budget across these tiers.

• Quantify how much PPA declared freedom actually opens on industrial, already hand-optimized designs compared to open-source designs.

• Publish at top-tier venues (e.g., DAC, ICCAD, ISCA, MICRO, ICLR, NeurIPS, ICML, Nature, Science), file patents, and contribute to shared & open-source tooling and benchmarks.

• Establish and maintain collaborations with our university research partners.

• At senior and principal level: shape the research agenda, own work packages end to end, and represent the work towards internal product teams and external partners.

Your background

• PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field, or equivalent research experience. For the senior and principal levels, several years of post-PhD experience in research or industry.

• Strong expertise in at least one of the following, and working knowledge of the others:

– Formal methods for hardware: equivalence checking (combinational and sequential), model checking, SAT/SMT, formal semantics of HDLs.

– Digital design and implementation: RTL design in SystemVerilog, logic synthesis, place-and-route, PPA optimization, with commercial or open-source flows (e.g., Yosys, OpenROAD, ABC).

– Hardware languages and compilers: hardware construction languages and intermediate representations (e.g., Chisel, CIRCT/MLIR, slang, Calyx, Filament).

– LLM-based agents for hardware or software engineering: tool use, context engineering, evaluation of agent output.

• Solid understanding of computer architecture (processor cores, accelerators, arithmetic units, memory systems).

• Strong programming skills in Python.

• A track record of publications at top-tier venues in EDA, formal methods, computer architecture or machine learning.

• Excellent written and verbal communication skills with a proven ability to present complex technical information clearly and concisely to a variety of audiences. Collaborative work style with the ability to work in a multicultural environment.

Why join us

• Collaborate with world-class scientists and engineers in an open, curiosity-driven environment.

• Push the research frontier and make a global impact through top-tier publications and open-source software, tools and flows.

• See your research applied to production circuits, in collaboration with the corresponding design teams around the world.

• Opportunities for professional growth and development.

• Competitive salary, and a high quality of life in Zurich, at the center of Europe.

• Last but certainly not least: be part of innovative projects that make a difference.

Applications need to include a CV and a motivation letter both merged in one document. Please indicate a range of possible starting dates in your motivation letter.