ASIC Static Timing and Synthesis Engineers (00005)

This is Harpal Singh and I am the Staffing Specialist with 22nd Century Technologies Inc. (TSCTI). We are Government Software integrators working with DoD and civilian space and are fast growing company in DoD sector with our Prime Contracts includes DLA, Peace Corp, Dept. of Navy, Dept. of Air Force, NIH, US Army, SSA, IRS, Dept. of Justice, Dept. of the Interior , Dept. of Transportation, Federal Maritime Commission, Broadcasting and over 35 States all over USA. 

Find more about us at www.tscti.com .

You can reach me at 908.765.0003 ext. 315 # for any questions, I’m available today till 6 PM EST.

Kindly send me your updated resume along with expected rates at singhh @ tscti.com 

Client: Northrop Grumman

Position: ASIC Static Timing and Synthesis Engineers (00005)

Work Location: Baltimore, MD

Duration: Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested) 

Clearance: Active Secret (No interim or inactive)

Job Description:

STA (Static Timing Analysis) Design Engineer

- looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

Responsibilities

- Work with systems architect/IP experts to develop level timing constraints

- Work with physical design team on design constraint and timing closure

- Be hands-on technical individual contributor

Requirements

- secret government clearance within last 5 years

- good knowledge of EDA tools and scripting

- BSEE with 8 years of experience or MSEE with 5 years’ experience in static timing & RTL Design

- Must be a very good team player with a very good oral, written and interpersonal communication skills

Tool experience 

- Synopsys Primetime-SI, Synopsys Design Compiler, Cadence Encounter Timing system

- Scripting languages – tcl, csh, perl, Makefile

- Operating systems: linux, window

- Revision control: SVN, git

Desirable 

- Experience with RTL synthesis

- Digital simulation, formal verification, linting, test insertion & atpg generation

- Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc

- Tool experience – Mentor Questa, Mentor Tessent, Synopsys Formality

Keywords

- STA, SSTA, OCV, Margins, Derates, Sign-off derate, PTV variation, sign-off criteria, STA methodology, sign-off methodology, binning

• secret government clearance within last 5 years\

• looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

All your information will be kept confidential according to EEO guidelines.