Job Title: Associate, FPGA / ASIC Verification Engineer
Job Code: 40384
Job Location: Cincinnati, OH
Job Schedule: 4/10: Employees work 10 hour days, 4 days a week
Job Description:
As an Associate ASIC/FPGA Verification Engineer at L3Harris you will be responsible for verifying the architecture, design and implementation of next generation Electronic Safe and Arm Devices utilizing the latest state of the art tools and technologies.
The ideal candidate for this role would share our passion for creating and innovating new technologies in a highly dynamic, fast-paced environment. We are looking for highly talented, motivated, and versatile engineers that can create the next generation fuzing solutions.
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A interfaces, communication protocols, state machines, timer chains, etc. used in Electronic Safe and Arm Devices (Fuzes) for DOD weapon systems. Microchip/Microsemi Antifuse and Flash are our targeted FPGAs with occasional ASIC development, Siemens Mentor Graphics QuestaSim Prime is our simulation tool, and the System Verilog UVM framework is the current verification environment. The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog UVM framework verification.
Essential Functions:
Qualifications:
Preferred Additional Skills:
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