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Design Verification Engineer, Principal

Job Description - Design Verification Engineer, Principal

Position Title: Design Verification Engineer, Principal (Confidential Client)

Location: Santa Clara, CA | Onsite

Employment Type: Permanent


Compensation



  • Salary: $158,600 - $317,800/yr

  • Additional Compensation: Base, bonus, RSUs, Refresher RSUs


Position Summary


As a leading member of the Network Switching team, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Your role may also include project management and leading a team of verification engineers on a project level.


Primary Functions



  • Verify all of the circuitry that goes inside chips for the general market and for specific customers

  • Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers

  • Write a verification test plan using random techniques and coverage analysis and work with designers to ensure it is complete

  • Develop tests and tune the environment to achieve coverage goals

  • Debug failures and work with designers to resolve issues

  • Verify boot code and architect, develop, and maintain tools to streamline the design of state-of-the-art multi-core SoCs

  • Transform the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment

  • Perform unit and regression testing of software tools

  • Lead a team of verification engineers on a project level


Must-Haves



  • BS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience)

  • Proven track record of leading Design Verification implementation activity and tape-out of complex SOC under tight schedule

  • In depth understanding and experience with System Verilog and UVM

  • In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment

  • Experience with scripting language such as Python or Perl and EDA Verification tools

  • Experience with Object-Oriented Design and implementation

  • Good understanding of Linux O.S.

  • Good programming skills, especially C++ and ARM assembly

  • Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision

  • Ability to accept and work with differing opinions

  • Able to learn on the fly and work in a fast-paced environment


Preferred Qualifications



  • Understanding of networking protocols

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