Lead Lab Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

As an Astera Labs Technical Lead Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions.  You will:

• Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions.  Collaborate with design, validation, and system engineering teams as needed.


• Modify device firmware to test out engineering theories leading to potential fixes or production screens.


• Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.


• Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.


• Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.


• Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.


• Develop and run stress tests and margining experiments to identify weak design or process corners.


• Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions).


• Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.


• Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.


• Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Basic qualifications:

• Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. 


• Minimum of 10 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.


• Python programming.


• Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.


• Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).


• Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).


• Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.


• Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.


• Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.


• Strong written and verbal communication skills.

Preferred experience (ideal candidate has some of this, but OJT is also possible):

• C (not C++).


• Experience with optics.


• Experience with chip-level security and RAS features.


• ATE (Automated Test Equipment) Advantest V93K.


• Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.