Physical Design Layout Lead Engineer

Company : Actsearch

Job Type : Full Time

Pleasanton, United States

Job Description - Physical Design Layout Lead Engineer

Description:

ï·Responsible for RTL to GDSII flow

ï·SDC/constrains understanding, generation, clock definition and timing closure

ï·Synthesis with industry standard EDA tools

ï·Low power analysis using UPF/CPF formats

ï·Place and Route, clock tree synthesis

ï·Static timing analysis

ï·Formal equivalence checks

ï·Layout verification and DRC analysis

ï·Static/Dynamic IR analysis, power analysis, reliability analysis

ï·Work with RTL engineers and tool vendor(s) for ongoing tool/methodology

improvement

Requirements

Physical Design (Layout) Lead

Qualification:

ï·MSEE with 10+ years of experience in implementation of ASIC/SoC in latest

process nodes

ï·Experience in Logic synthesis, DFT insertion, STA, physical design, layout

verification and Tapeout

ï·Proven track record in resolving PD issues like placement, congestion, CTS, routing

ï·Good understanding of timing convergence process

ï·Conversant with low power design implantation, IR/EM analysis

ï·Hand on experience with industry standard place and route EDA tools (preferably

Cadence)

ï·Experience handling tapeouts

ï·Prior experience working for startups highly desirable

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Physical Design Layout Lead Engineer

Job Description - Physical Design Layout Lead Engineer

Requirements

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