Design, simulate, and optimize DRAM memory array, data path, ECC, command/control, and high‑speed interface circuits Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM or mixed‑signal circuits Perform pathfinding and feasibility studies to explore new architectures for future HBM products Contribute to the design, layout, and optimization of memory, logic, and analog circuits Support verification, debug, and validation activities for large‑scale HBM designs Work collaboratively across engineering teams involved in vertical integration and TSV‑based stacking Participate in design reviews and continuous improvement of design methodologies BSEE with 7+ years, or MSEE with 5+ years of relevant engineering experience Extensive knowledge of CMOS circuit design and device physics Experience with schematic entry and simulation using FineSim, HSPICE, or equivalent tools Proficiency with scripting languages such as Python, Tcl, or Perl Familiarity with memory design Effective communication skills and an innovative mindset open to improving processes and products We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. To learn about your right to work click here. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
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