Staff Memory Design Engineer, DRAM

Design, optimize, and validate memory, logic, and analog circuits Model parasitics and support design validation, reticle experiments, and tape‑out revisions Guide and manage physical layout, including floor‑planning, placement, and routing Perform modeling and simulation using industry‑standard tools Collaborate across teams to improve design quality and ensure manufacturable solutions BS or MS in Electrical Engineering or related field plus 6 years of experience in DRAM design, product, or system Coursework in CMOS circuit design, VLSI, and digital circuit design Experience with Cadence Virtuoso Understanding of physical layout, circuit floor planning, and device reliability Experience using FINESIM, HSPICE, and VERILOG Strong problem‑solving skills with curiosity for new approaches Deep knowledge of industry‑specific technologies and trends Excellent communication and collaboration skills Expertise in DRAM subsystem architecture, specification, operation, or design