Staff Verification Design Engineer, DRAM

Develop and complete comprehensive verification plans for sophisticated memory builds, with a strong focus on DRAM products Perform circuit simulations using tools such as HSPICE, SPICE, Verilog, and Timing Accurate Verilog (TAV) Support array parasitic extraction and drive the development of corresponding modeling cells Coordinate planning and review of layout‑extracted netlists for critical circuits Contribute to global Design and Verification Methodology Forums Collaborate closely with Business Units, Product Engineering, Probe, Assembly, Test, Process Integration, and CAD teams to ensure manufacturability and successful product ramp Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with equivalent professional experience accepted Minimum 7 years of proven experience in verification or related design roles Strong background in verification leadership and project coordination Hands‑on experience with UVM and SystemVerilog Assertions (SVA) Solid understanding of memory/DRAM architectures and verification challenges Proficiency with HSPICE and Python (required) Strong understanding of circuit simulation setup, analysis, and debug Excellent written and verbal communication skills, with the ability to convey sophisticated technical concepts to both technical and non-technical partners Experience with Design for Test (DFT) methodologies for memory products Exposure to RTL verification, Static Timing Analysis (STA), and Timing Accurate Verilog (TAV) Experience with silicon validation, test chip bring‑up, or post‑silicon debug Demonstrated ability to mentor engineers and influence verification strategy across global teams Strong motivation to grow technical breadth and depth within a collaborative, fast‑paced environment