DFT Intern

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

About the Role

We’re looking for a Design for Test (DFT) Intern to join our SoC team and contribute to scan and MBIST implementation and verification for our ultra-low power chips. In this role, you’ll gain hands-on experience with industry standard DFT tools and methodologies, learn how to improve manufacturing test coverage and test quality, and work alongside experienced engineers designing edge AI products. This internship is an excellent opportunity to apply what you’ve learned in class, explore industry-standard tools, and see how your work connects to the technology powering everyday devices. 

Responsibilities

As a DFT Intern, you will:

• Support low power DFT implementation and verification for SoC designs


• Assist with scan insertion, scan chain verification for physical design modules


• Assist with MBIST insertion and verification for embedded memories


• Analyze DFT rule checking results and help resolve design and testability issues


• Support test coverage analysis and identify opportunities for coverage improvement


• Develop and maintain scripts (e.g., Tcl, Python, Shell) to automate recurring tasks and improve engineering productivity


• Document methodologies, results, and key learnings, and present progress to your mentor and the broader team


• Collaborate with RTL, DFT, DV, and physical design engineers to debug implementation, coverage, and timing issues

Qualifications

• Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field


• Completed coursework in several of the following areas:
  
  
  
  • Digital logic design
  
  
  • VLSI design / ASIC design
  
  
  • CMOS circuits
  
  
  • Computer architecture (preferred)
  
  
  
  


• Familiarity with Verilog, SystemVerilog or VHDL and fundamental digital design concepts such as timing, clocking, reset, and pipelining


• Comfortable working in a Linux/UNIX environment


• Strong analytical, debugging, and problem-solving skills


• Good communication skills and a collaborative mindset

 Preferred Qualifications

• Experience (coursework or project or internship) with industry-standard EDA tools for:
  
  
  
  • Scan insertion or ATPG
  
  
  • MBIST, memory repair, or embedded memory testing
  
  
  • ASIC design, or synthesis
  
  
  
  


• Basic understanding of DFT concepts such as scan, ATPG, MBIST, fault coverage, and memory repair


• Exposure to industry standard EDA tools


• Scripting experience in Tcl, Python, or Shell for flow automation


• Familiarity with fault models such as stuck-at, transition, bridging, memory faults


• Understanding of low power design concepts such as multiple power domains, retention, or clock gating