Digital Engineer

Deine Rolle im Team

• Experience in building verification environments using UVM methodology
• Execute the pre-silicon verification of digital and/or mixed-signal products
• Create verification plans using datasheets, inputs from engineers / customers, and working closely with systems engineers
• Implement automatic checks and measurements to verify behavior and populate a Specification Matrix
• Define and implement functional coverage and drive coverage closure
• Provide periodic updates on DV status to project participants, management, and customers.
• Work with design and systems teams to close bugs as they arise.
• Bug tracking, functional coverage, RTL code coverage

Technologien und Skills

• SystemVerilog

Unsere Erwartungen an dich:

Qualifikationen

• Advanced verification methodologies such as UVM
• Development of testbench concept and testbench architecture
• Knowledge of Verification Languages (e.g. SystemVerilog, Specman, 'e', etc)
• Team Player
• Knowledge of semiconductor physics and semiconductor technologies
• Good verbal and written English skills, German is an advantage

Erfahrung

• Several years of professional experience in Digital Verification
• Experience with the CAD tools and methods

Ausbildung

• Bachelor or Master degree or equivalent in electrical engineering or physics