Advanced characterization and understanding of 2D FETs

Motivations

Performanceand scalability of MoS₂ FETs are strongly constrained by contact resistance,Fermi-level pinning, and gate-stack limitations such as interfacetraps, dielectric deposition challenges, and high operating voltages. Improvingboth the contact interface and the gate dielectric stack isessential for enabling low-power, high-performance 2D electronics. [arxiv.org],[science.org]

Objectives

Thecandidate will participate in the following research activities at IMEC:

1. Engineer low-damage, low-resistance contacts using metals with favourable interaction to MoS₂ (e.g., Ni, Ti, Y) by studying interface chemistry, band alignment, and deposition-induced defects.
2. Develop high-quality gate stacks using ultra-thin high-κ dielectrics (Al₂O₃/HfO₂/ZrO2). Correlate structural, electrical, and thermal reliability up to compatible BEOL temperatures.
3. Provide support on electrical characterization and modelling of ferroelectric memories (FeFET and FeRAM).

Requirements:

1. Background in Electrical engineering, semiconductor physics, quantum physics, semiconductor device reliability.
2. Experience with electrical characterization of electronic devices.
3. Experience in semiconductor industry.
4. Internship up to 1 year, self-supported PhD student.

Type of internship: PhD internship

Duration: up to 1 year

Required educational background: Electrotechnics/Electrical Engineering

University promotor: Clement Merckling (KU Leuven)

Supervising scientist(s): For further information or for application, please contact Bogdan Govoreanu ([email protected]) and Xiangyu Wu ([email protected]) and Nicolo Ronchi ([email protected])

The reference code for this position is 2026-INT-040. Mention this reference code in your application.

Only for self-supporting students.

Applications should include the following information:

• resume
• motivation
• current study

Incomplete applications will not be considered.