Design Space Exploration of Emerging 3D Stacking Solutions for High-Bandwidth Memory

Advanced packaging technologies such as 3D stacking, silicon interposers, and hybrid bonding are reshaping the capabilities of high-bandwidth memory. However, these innovations introduce complex co-dependencies among bandwidth, capacity, power, and form factor. This internship aims to create a systematic design space exploration framework for emerging 3D HBM packaging options. The student will model and evaluate packaging parameters including stack height, TSV density, bonding pitch, cooling and power delivery strategies. The resulting exploration platform will quantify performance, capacity, energy, and area, enabling informed decisions for next-generation 3D HBM integration in AI accelerators and heterogeneous SoCs.

Skills to stand out:

• Solid understanding of memory subsystem
• Familiarity with different bit cell concepts and RC delay modeling
• Strong programming skills in C++ or Python
• Experience with performance modelling techniques
• Exposure to system-level simulation tools or benchmarking frameworks is a plus (Ramulator, DRAMSys, DRAMSim, Gem5, ...)

Type of internship: Master internship, PhD internship

Duration: 6-9 months

Required educational background: Computer Science, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology

Supervising scientist(s): For further information or for application, please contact Khakim Akhunov (< email deleted for security reasons >)

The reference code for this position is 2026-INT-044. Mention this reference code in your application.

Imec allowance will be provided for students studying at a non-Belgian university.

Applications should include the following information:

• resume
• motivation
• current study

Incomplete applications will not be considered.