Design Verification Engineer System Verilog

Role: Design Verification Engineer System Verilog

Location: VANCOUVER, BC

Duration: Fulltime

Key Responsibilities

• Utilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.
• Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.
• Conduct full-chip and SoC simulations to validate design functionality and performance.
• Demonstrate expertise in subsystem verification, encompassing controllers and PHY components.
• Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality.
• Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe.
  
  

Thanks and Regards

Megha Khare

Team Lead

P: (647) 905-8179 | E: [email protected]

LinkedIn: https://www.linkedin.com/in/megha-khare-9485b497/

110 Matheson Blvd W, Mississauga, ON L5R 3R3

https://www.epsilonsolutions.ca/careers/

Disclaimer

Epsilon solutions provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability.