Sr. Staff Power Integrity Engineer

About this Role

Lightmatter is looking for a Power Integrity engineer to drive the next generation products from concept to development. As part of a cross-functional systems and packaging team—including silicon, package, and systems engineers—you will drive the definition, optimization, and completion of package and system architecture to meet the product’s power integrity requirements. This role presents a unique opportunity to innovate new package and system architectures, solving complex interaction across digital, analog, and photonics domains while achieving stringent signal and power integrity goals. 

Responsibilities:

• Design the end-to-end Power Delivery Network (PDN) for digital and analog SoC domains, from the voltage regulator to the on-chip decoupling.


• Model voltage regulator switching ripple, bandwidth, and transient response and aid in the selection of power stages, controllers, and associated passives.


• Simulate PCBs and packages in commercial 2.5D electromagnetics simulators to extract N-port models and subsequently, impedance profiles. 


• Perform time domain simulations of supply rails to characterize worst case droops and overshoots.


• Conduct detailed power integrity measurements and characterization using lab equipment, for example, using programmable loads to measure the transient response of the power delivery network.


• Collaborate with cross-functional teams, including hardware designers, PCB layout engineers, system architects, and power and performance engineers, to provide power integrity guidance and support throughout the product development lifecycle.


• Contribute to power integrity design reviews, providing technical expertise and recommendations to ensure optimal power integrity performance and adherence to design specifications.


• Document and communicate analysis results, design guidelines, and recommendations to stakeholders, including design teams, management, and customers.


• Participate in cross-functional teams to define and influence system-level architecture decisions that impact power integrity, ensuring optimal performance and scalability.

Requirements: 

• M.S. or Ph.D. in Electrical Engineering or a related field.


• 14+ years of related experience with a Bachelor’s degree, 12+ years with a Master’s or 8+ years with a Ph.D. in power delivery and power integrity analysis for high performance CPUs and compute SoCs. 


• Proficiency in using simulation and analysis tools for power integrity, including PowerSI, PowerDC, H-Spice and ADS. 


• Experience in DC-DC converter design.


• Experience with PCB design and layout considerations for power integrity, including layer stack-up assignment, power plane partitioning, capacitor selection and placement, and microvia/PTH design.


• Strong problem-solving and debugging skills for power integrity-related issues.

Preferred Qualifications: 

• Working knowledge of different 2D/2.5D/3D packaging technologies and associated PDN challenges.


• Familiarity in using lab equipment for signal measurement and characterization, such as oscilloscopes and network analyzers.


• Proficiency in scripting languages such as Skill, TCL, Python, and Matlab for automation of design and modeling flows and post-processing results