Staff ASIC Verification Engineer, Low Power AI Subsystems

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

What we are doing has not been done.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

We are looking for a Staff ASIC Verification Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications.

Verification tasks will include:

• Contribute to core verification during the pre/post silicon phase of next generation ASICs through simulation
• Drive test plan development, execution and verification closure in conjunction with the design and verification teams
• Contribute to creating/maintaining a test bench, assertions, and functional coverage models with scalability and reuse as key goals
• Contribute to implementing flows to automate development processes. Identify areas for improvement and drive them to completion
• Lead complex debug activities through the development cycle (pre and post-silicon)
• Provide technical supervision to other engineers and have the ability to lead by example
• Work closely with design to define verification methodology, Provide test plans and develop required tests.

Specific responsibilities will be a function of project and team needs and may vary over time.

Requirements:

• Min 4+ years ASIC design, verification, implementation or related work experience
• Expert Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
• Deep understanding of ASIC/VLSI concepts
• Expert hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC,
• Expert hardware description languages (HDL): Verilog and/or SystemVerilog
• Good working experience with C (basic level or C++ sufficient)

Preferred Qualifications:

• Knowledge in one or more of the following disciplines is preferred: Audio (MP3, MIDI, etc.),  Bus/interconnect (AHB, AXI), CPU (ARM v8/v7, Cache, MMU, security, etc.).
• Strong knowledge of digital circuits and event-driven simulators
• Knowledge of Perl, tcsh, Python and GNU Make is a strong asset
• Experience with automotive safety concepts and standards such as ISO26262

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