MEMS - Digital Verification - SR/Team Leader

OUR STORY\n\n \n\n\nAt STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.\n\n \n\n\nWhen you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.\n\n \n\n\nDeveloping technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential. \n\nEmbark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.\n\nYOUR ROLE \n \nThe position is aimed at Digital Verification engineer with previous experience in digital verification of ASIC. \n \nThe candidate will join the digital verification team of MEMS sGROUP and he/she/div will have the opportunity to see all the ASIC verification process from specification definition up to final product industrialization. \n \nHis/her/div responsibilities includes definition and development of verification testbench, development of verification components, development of DSP models and digital control logic, test case development for simulation, debugging failures and creating simulation cases for various scenarios.\n\nThe position is open on Toulouse (France) sites. We are looking for Senior Profiles/Team Leader.\n\nYour Skills \u0026 Experiences \n \nThe preferred seniority is 3 to 5 years of experience.\n\n * Background in digital verification testbench (Universal Verification Methodology and System Verilog ), knows System Verilog and has experience with digital simulator tools.\n * Universal Verification Methodology, System Verilog Assertion, coverage, self-checking capabilities, testbench automation, bugs analysis and reporting.\n * Requested basic knowledge of python scripts, TCL scripts, version control system.\n * A plus will be considered the knowledge of formal verification and communication protocols (e.g. I2C, SPI and I3C).\n * The candidate has also soft skills such as good communication, fluently in English, team working and collaboration across all the entire MEMSs GROUP Design team.\n\n\n\nST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics \u0026 integrity, purpose \u0026 values, organization \u0026 change, business strategy, and performance.\n\nAt ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. \n\n \n\n\nTo discover more, visit st.com/careers.\n