Senior NoC Research Engineer (Network-on-Chip)

We are seeking a Senior Network-on-Chip (NoC) Research Engineer to shape the on-chip and chip-to-chip interconnect of SpiNNext, our next-generation chip. In systems built from very large numbers of cores, moving data efficiently determines both performance and energy efficiency. You will model, simulate and evaluate interconnect architectures under real ML workloads, and turn your findings into quantitative design decisions. You will report to our CTO and work closely with our chip architecture, hardware and software teams.

Education & Experience

• PhD, or Master's with equivalent research experience, in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Senior-level track record in NoC or interconnect architecture, in industry or applied research

Technical Skills

• Strong background in on-chip interconnect and traffic management: NoC topologies, routers and switches, arbitration, flow control, QoS and congestion control
• Good understanding of ML workloads and accelerator architectures, including how collective communication, tensor parallelism and memory traffic stress the interconnect
• Working knowledge of on-chip protocols such as AXI, CHI or AHB
• Understanding of RDMA concepts and transports (InfiniBand, RoCE), including queue pairs, memory registration and zero-copy transfers
• Experience reasoning about PPA trade-offs with quantitative evidence
• Hands-on architectural modelling and simulation (SST, gem5 or own models), with strong Python and C++
• Ability to read complex protocol and IP specifications and turn them into clear design requirements
• Experience with deadlock and livelock avoidance, adaptive routing or topology exploration
• Clear written and verbal communication in English, and a proactive, collaborative approach to open-ended problems

• Competitive salary based on experience
• 30 days annual vacation, up to 2 weeks of work abroad
• Work on cutting-edge sparse computing technology
• High-impact role with direct influence on the architecture of SpiNNext
• Collaborative team culture with experienced engineers from academia and industry
• Equity participation in a growing deep-tech company