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The future of AI computing is light, not electrons. Q.ANT is building photonic processing systems that compute with light – delivering a scalable, energy-efficient alternative to transistor-based architectures for next-generation AI and HPC applications.
As Senior GHz Analog & Mixed-Signal Engineer (m/f/d), you are the architect of the high-speed electronic signal paths in the GHz-range that make photonic computing real. You will design, simulate, and validate circuits that interface directly with cutting-edge silicon photonic devices, custom ASICs, and advanced 2.5D/3D interposer platforms. Working at the intersection of RF electronics, electro-optics, and semiconductor heterogeneous integration, you will turn individual high-performance components into unified, scalable subsystems.
Your Responsibilities
- High-Speed Analog & Mixed-Signal Design: Specify, design, and simulate GHz-band circuits including TIAs, ADC/DAC front-ends, amplifiers, and PLLs – optimizing for noise, linearity, jitter, bandwidth, and power efficiency using tools such as SPICE, SpectreRF, and ADS.
- Electronic-Photonic Co-Design: Define and optimize electrical-optical impedance matching, biasing, and signal conditioning for silicon photonic components including modulators, photodetectors, and waveguide interfaces.
- Interposer & Advanced Packaging Integration: Develop and validate 2.5D/3D integration architectures using interposers and chiplets; co-simulate RF parasitics, TSV routing, and thermal behavior to ensure signal integrity across heterogeneous boundaries.
- ASIC Collaboration: Partner with ASIC designers to define high-speed interface requirements and support SerDes, CDR, and mixed-signal block integration.
- Lab Bring-Up & Validation: Lead hands-on characterization of electro-optic bandwidth, eye diagrams, jitter, noise spectra, and system-level behavior using oscilloscopes, VNAs, BERTs, and spectrum analyzers.
- Innovation & IP Contribution: Propose novel analog architectures and co-integration strategies that push beyond conventional design limits, contributing to Q.ANT's IP portfolio and next-generation photonic processor roadmap.
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