Master Thesis / Working Student Mixed-Signal Modelling and Design Verification

OUR STORY\n\n \n\n\nAt STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.\n\n \n\n\nWhen you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.\n\n \n\n\nDeveloping technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential. \n\nEmbark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.\n\nYOUR ROLE \n\nYou take part in creating the best new hire experience in the project to completely renew our talent acquisition and onboarding process. You also help us with finding the best vendors for recruitment, and managing the a to z collaboration with them.\n\n * We are looking for a motivated student to join our Power Management IC Design Verification Team. In this role, you will actively contribute to IC top-level verification tasks and flow development. Your work will focus on enhancing verification flows in line with the latest advancements in Mixed-Signal top-level verification and analog behavioral model development. These improvements will adhere to IEEE/Accellera standards and leverage the reference manuals of leading Electrical Design Automation (EDA) tools and flows.\n * You will also collaborate closely with EDA vendors such as Cadence, Synopsys, and Mentor, gaining hands-on experience in cutting-edge verification methodologies.\n * This position offers a unique opportunity to explore, understand, and implement innovative verification concepts in a productive and impact way.\n\n\n\n\nYOUR SKILLS \u0026 EXPERIENCES\n\n * Degree in Electronics or similar course of studies. \n * Basic understanding of analog circuits and simulators.\n * Familiarity with Cadence design flows.\n * Understanding Hardware description languages (Verilog, SystemVerilog).\n * Strong programming skills, particularly in Python.\n * Knowledge of Virtuoso SKILL language is a plus.\n * A willingness to learn, understand, and apply new concepts.\n\n\n\n\nST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics \u0026 integrity, purpose \u0026 values, organization \u0026 change, business strategy, and performance.\n\nAt ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. \n\n \n\n\nTo discover more, visit st.com/careers.\n