Physical Design Lead

Fortune 500 company

location: Bangalore

Job Overview: As a Backend Technical Lead specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconductor designs. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs.

Key Responsibilities:

1.Project Planning and Execution: Develop and maintain project plans, timelines, and milestones for back-end design phases of chip design. Coordinate with engineering teams to ensure project goals are clearly defined and aligned with overall business objectives. Monitor and manage project progress, identifying potential risks and implementing mitigation strategies.

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2.Stakeholder Communication: Communicate project status, risks, and milestones to internal and external stakeholders.

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3.Documentation: Maintain accurate and up-to-date project documentation, including design specifications, test plans, and progress reports. Ensure compliance with industry standards and regulations.

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4.Continuous Improvement: Identify opportunities for process improvement and efficiency gains in the chip design workflow. Stay informed about industry trends and emerging technologies.

Key Responsibilities (continued)

5. Synthesis : Oversee the process of Synthesis for correct translation of RTL to gate-level. Address feasibility for performance, power and area, managing clock gating, multi-Vth, library components.

6. Physical Design and Optimization: Oversee floor-planning, placement, and routing activities for digital components to optimize for area, power, and performance.

7. Timing Closure and Signal Integrity: Lead efforts to achieve and maintain timing closure through iterative optimizations. Address signal integrity issues through careful analysis and design adjustments. Expertise in Static Timing Analysis (STA) to ensure that the chip meets timing requirements.

8. Clock Tree Synthesis (CTS) and Power Distribution Network (PDN):Manage the design and optimization of clock distribution networks. Ensure the robustness and efficiency of the power distribution network by addressing issues such as IR-Drop/Voltage Droop.

9. Physical Verification: Oversee physical verification processes, including Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checks, Electro-Static Discharge (ESD) check, and Electrical Rule Check (ERC).

10. Formal Verification: Oversee Formal Verification(FV) methods to mathematically prove the logic equivalence with implementation design and reference RTL.

11. Technology Node Migration: Navigate and adapt designs to different technology nodes, ensuring compatibility and leveraging advancements.

12. Multi-Voltage Design: Manage designs with multiple voltage domains(multi voltage, power shut down), incorporating and verifying level shifters, isolation and power switch techniques.

13. Hierarchical Design and IP Integration: Oversee the optimization of hierarchical designs for scalability and ease of integration. Coordinate the integration of third-party Intellectual Property (IP) blocks.

14. Tapeout Process: Guide the team through the tapeout process, collaborating with foundries for successful chip fabrication.

15. Place and Route Optimization: Proficiency in optimizing the placement and routing of digital components for improved performance and manufacturability.

16. EDA Tools for Back End: Expertise in using Electronic Design Automation (EDA) tools specific to back-end design stages.

17. Post-Silicon Debugging: Ability to analyze and address issues that may arise during the post-silicon validation phase.

Key Responsibilities (continued)

18. Packaging and Assembly Considerations: Awareness of packaging and assembly constraints and collaboration with packaging engineers for seamless integration.

19. Design for Manufacturing: Oversee Design For Manufacturing(DFM) methods Double-cut-Via, Dummy metal and other DFM aspects.

20. DFT : Oversee Design For Test(DFT) methods Memory BIST, Scan, IP test. Incorporating and verifying test circuit preserving the original functionality with comprehensive coverage and minimal overhead. Manage design constraints for DFT, ATPG test patterns, Diagnosis, FBM.

21. Product Support for Pre-production : Create test patterns from system-level simulations to ensure comprehensive testing coverage in the Pre-production phase. Collaborate with system architects and designers to validate system-level functionality and address any issues before moving to production. Facilitate the smooth transition of designs from the development phase to the manufacturing phase.

22. Product Support for Post-production: Address customer concerns and troubleshoot issues related to the semiconductor products post-production. Conduct customer-requested simulations to validate specific functionalities and address customer-specific requirements. Perform return failure analysis to identify root causes of issues reported by customers and collaborate with cross-functional teams to implement corrective actions.

Qualifications:

• Masters in VLSI design from reputed universities like IIT/NIT with background in Bachelors in Electronics and Communication, or a related field.

• 7+ years of experience in the field of semiconductor chip design.

• Proven experience in project management, with a focus on the back-end stages of semiconductor chip design.

• Strong technical background in physical design and back-end processes.

• Excellent leadership and communication skills.

• Familiarity with project management tools and methodologies.

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Preferred Skills:

• Project Management Professional (PMP) certification is a plus.

• Experience with Electronic Design Automation (EDA) tools specific to back-end design.

• Knowledge of industry standards and best practices in semiconductor back-end design.

• Familiarity with Agile methodologies.

Contact

Uday

Mulya Technologies

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