Analog Layout Engineer

This role is for one of the Weekday's clients

Salary range: Rs 2000000 - Rs 6500000 (ie INR 20-65 LPA)

Experience: 5+ yrs

Location: Bengaluru, Germany

Job Type: Full-Time

We are seeking an experienced Analog Layout Engineer to join a dynamic semiconductor engineering team working on advanced Analog, Mixed-Signal, IO, and Memory designs. This role offers the opportunity to contribute to cutting-edge custom layout development across leading technology nodes while collaborating closely with circuit designers and verification teams to deliver high-quality silicon solutions.

The ideal candidate will have strong expertise in Analog Custom Layout, physical verification, and layout optimization, with hands-on experience using industry-standard EDA tools to ensure design quality, reliability, and manufacturability.

Key Responsibilities

• Develop high-quality custom layouts for Analog, Mixed-Signal, IO, and Memory IPs.
• Collaborate closely with circuit design, verification, and physical design teams throughout the development cycle.
• Perform layout optimization to meet performance, area, reliability, and manufacturability requirements.
• Execute physical verification activities, including DRC, LVS, and ERC checks, and resolve related design issues.
• Create production-ready layouts using Cadence Virtuoso while adhering to layout best practices and foundry guidelines.
• Analyze and resolve layout-related challenges to ensure first-pass silicon success.
• Support layout reviews, design rule compliance, and signoff activities.
• Work with cross-functional engineering teams to achieve project milestones and delivery schedules.
• Contribute to continuous improvement of layout methodologies, automation, and design quality.
• Ensure layouts comply with technology-specific requirements and advanced process design rules.

What Makes You a Great Fit

• Proven experience in Analog Layout and Custom Layout development for semiconductor designs.
• Strong hands-on expertise with Cadence Virtuoso and Calibre for layout implementation and physical verification.
• Solid understanding of DRC, LVS, ERC, and overall physical verification methodologies.
• Experience developing Analog, Mixed-Signal, IO, or Memory layouts in advanced semiconductor technologies.
• Strong knowledge of layout optimization techniques for performance, matching, reliability, and manufacturability.
• Experience working with technology nodes of 40nm and below is preferred.
• Exposure to Mixed-Signal Layout, FinFET technologies, or TSMC advanced process nodes is an added advantage.
• Excellent debugging, analytical, and problem-solving skills with attention to layout quality and detail.
• Strong collaboration and communication skills with the ability to work effectively in cross-functional engineering teams.
• Passion for solving complex layout challenges and delivering high-quality semiconductor solutions in a fast-paced development environment.