Analog Layout Engineer / Lead

We’re looking for strong Analog Layout Engineers to drive custom layout implementation for analog/mixed-signal and custom-digital blocks within a full SoC flow. You’ll own end-to-end layout execution, ensuring clean physical verification (DRC/LVS) and high-quality tapeout readiness. The role involves detailed floorplanning, routing, and handling critical constraints like matching, parasitics, signal integrity, and power distribution.

You’ll work closely with analog design teams to align on trade-offs, performance, and schedules, while also mentoring junior engineers and reviewing layouts for quality. Hands-on expertise in Cadence Virtuoso LayoutXL and Mentor Calibre is essential. Strong experience in FinFET or planar CMOS technologies is required, with exposure to SiGe or GaN as a plus.

Candidates should bring solid experience in chip-top/PAD ring layout and integration of analog IPs with digital GDS. Knowledge of DFM principles and the ability to debug complex layout issues is expected. Experience in high-speed domains like SERDES, RF, or PMIC layouts will give you an edge.