Analog/Mixed-Signal IC Design

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

• Bachelor’s degree or advanced diploma in Electrical Engineering (EE)

• 8+ years of experience in high-speed analog IC layout using Cadence Virtuoso


• Prior experience with BiCMOS layout is strongly preferred


• Proven experience handling at least one chip top-level through tapeout


• Proficiency in layout extraction and parasitic analysis for high-speed circuits


• Awareness of EMIR and antenna DRC rule-compliant layout practices


• Experience with Cadence SKILL and TCL scripting is highly recommended

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.