ASIC Design Verification Manager

To be part of a highly skilled ASIC Team working on latest technologies Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off Ability to lead and mentor a team of verification engineers Ensure first pass product through verification coverage and sign-off criteria Pair with similar domain specialists across other geographical locations on core technical initiatives M.S./M.Tech, BS/BE (Electronics) with 10+ Years of experience Strong experience with PCIe5-6-7/NVMe protocols is a MUST, familiarity with NAND is a plus Proven track record of building Verification Plan, UVM Environment and Test Benches Experience with RTL debugging, Scoreboard, Assertions, Functional coverage coding and Code Coverage analysis Sound knowledge of Verilog and System Verilog languages This position requires good written and verbal communication skills as well a strong commitment and ability to work in cross functional and global teams PCIe protocol knowledge and work experience on PCIe Endpoint verification