CPU STA/Timing Engineer (Lead/Staff/Sr Staff)

## \nCompany:\n\nQualcomm India Private Limited\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e Hardware Engineering\n\nGeneral Summary:\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what\u0027s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. \nOR \nMaster\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. \nOR \nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Overview:\n\nAs a CPU Physical Design Timing (STA) Engineer, you will be a key contributor to high\u2011performance CPU core and uncore designs, working closely with CPU microarchitecture, RTL, CAD, and physical design teams. \nYou will drive timing analysis and closure for complex, multi\u2011GHz CPU designs across block, cluster, and full\u2011chip hierarchies, ensuring aggressive frequency and power targets are met.\n\n## \n\n## Roles and Responsibilities\n\n * Work closely with CPU microarchitecture, RTL, and DFT teams to understand CPU pipelines, critical paths, and performance goals, and to define, implement, and validate timing constraints.\n\n * Perform STA for high\u2011performance CPU designs at block, cluster, and SoC/top\u2011level hierarchies across multiple modes, corners, and scenarios.\n\n * Analyze timing on frequency\u2011critical CPU paths (core, cache, interconnect, clocking) and collaborate with RTL and DFT teams to drive logic and micro\u2011architectural fixes.\n\n * Provide actionable timing feedback to block\u2011level and top\u2011level physical design engineers to enable CPU frequency and timing closure.\n\n * Partner with CAD and methodology teams to develop, deploy, and enhance CPU\u2011specific timing flows and infrastructure.\n\n * Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross\u2011talk violations in CPU designs.\n\n * Contribute to CPU timing methodology definition, best practices, and documentation for consistent signoff quality.\n\n\n\n\n## \n\n## Preferred Qualifications\n\n * MS degree in Electrical Engineering with ~6+ years of hands\u2011on experience in STA and timing closure.\n\n * Strong experience with STA and timing closure for high\u2011performance CPU or processor\u2011class SoCs.\n\n * Expertise in multi\u2011clock, multi\u2011domain CPU designs with aggressive frequency targets.\n\n * Experience in deep sub\u2011micron technology nodes and advanced process technologies.\n\n * Proven experience performing STA on large CPU/SoC designs with multi\u2011scenario and signoff\u2011quality closure.\n\n * Hands\u2011on knowledge of timing ECO techniques and their implementation for CPU frequency closure.\n\n * Solid understanding of standard cell libraries, CPU\u2011critical path optimization, and timing trade\u2011offs.\n\n * Familiarity with circuit modeling, transistor fundamentals, and worst\u2011case corner selection for CPU timing signoff.\n\n * Strong understanding of industry\u2011standard synthesis, place \u0026 route, and tape\u2011out flows.\n\n * Excellent communication skills to work effectively with CPU architects, RTL designers, PD, and CAD teams.\n\n * In\u2011depth knowledge of timing effects such as noise, cross\u2011talk, OCV/variation, and their impact on CPU designs.\n\n * Working knowledge of CPU/SoC architecture and HDL languages such as Verilog.\n\n\n\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm\u0027s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. 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