Design Methodology Principal DRAM Power Integrity Engineer

Req. ID:\n\nJR97282 Design Methodology \u2013 Principal DRAM Power Integrity Engineer\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities:\n\n * Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes\n * Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry\u2011standard tools; identify root\u2011cause issues such as high\u2011resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams.\n * Actively leverage AI\u2011based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis.\n * Maintain a strong understanding of the full EMIR flow\u2014from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation\u2014and ensure accurate evaluation across operating modes and temperatures.\n * Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst\u2011case vectors, and standardize analysis expectations across global teams.\n * Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams.\n * Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs.\n\n\n\nQualifications:\n\n * Master\u2019s degree in electrical or computer engineering. \n * 8 - 14 years of experience in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.\n * Deep hands\u2011on experience with Ansys RedHawk or Totem for full\u2011chip EM/IR verification and PDN analysis, including setup, scenario creation, debug, and root\u2011cause analysis.\n * Expertise in vectorless and dynamic/pattern\u2011based IR\u2011drop analysis, with strong ability to interpret current behavior, switching activity, and voltage\u2011sensitivity trends.\n * Proven ability to identify root causes of IR\u2011drop issues\u2014including switching activity, grid resistance, parasitics, routing topology\u2014and translate analysis results into actionable design or layout fixes.\n * Experience performing SoC\u2011level or chip\u2011level EMIR signoff and supporting tapeouts.\n * Solid understanding of PDN interactions with circuit timing/margin, layout topology, and chip\u2011level power architecture.\n * Ability to understand the full end\u2011to\u2011end design flow, including RTL, floorplanning, routing, extraction, EMIR, STA, and silicon correlation.\n * Familiarity with Make or similar automation frameworks for EMIR rollups.\n * Hands\u2011on experience with low\u2011power, multi\u2011voltage, power\u2011off, or mixed\u2011signal designs.\n * Experience in chip\u2011level IR/EM analysis and driving closure across multi\u2011functional teams.\n\n\n\nPreferred Qualifications:\n\n * Experience with power\u2011modeling or current\u2011source modeling flows (e.g., CPM).\n * Scripting skills in Python/Tcl for automation and data analysis.\n * Experience in improving EMIR/PI analysis flows or methodology.\n * Knowledge of PnR or STA tools (FusionCompiler, PrimeTime).\n * Background in circuit design with SPICE experience.\n * Exposure to or strong interest in AI/ML-assisted design flows, agentic AI or advanced automation in circuit design and verification.\n * Familiarity with memory\u2011product power behavior (DRAM/SRAM/NAND).\n\n\n\nJob Profile(s):\n\nSemiconductor Design Engineer 5\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n