DFT Engineer

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI

hardware is built for the future.

We are actively seeking a resourceful DFT Engineer based in Hyderabad OR Bangalore

Key Responsibilities:

• Hierarchical MBIST and scan insertion, BSD implementation


• ATPG pattern generation, coverage analysis, converging to high coverage metrics


• Pattern simulations with timing


• Defining test mode timing constraints, analyzing the timing reports and converge timing


• Developing cycle accurate functional patterns using IJTAG methodology


• Closely working with the test and production engineering teams to debug and bring up devices at probe and final test


• Debugging silicon issues

Skills:

• Excellent communication skills, and strong team player with can do type of attitude


• Excellent debugging skills


• Good scripting skills to develop automation

 Qualifications:

• 5+ years of DFT experience including implementation, test pattern development, and simulation


• Proven experience in contributing to DFT solution to complex designs


• Experience working with IJTAG methodologies


• Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies


• Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics


• Good debug capabilities in simulating patterns with timing


• Experience with industry standard EDA tools for DFT, timing, and simulation


• Knowledge of System Verilog

Education:

• Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/