Engineering Manager (Analog ASIC Design)

About Vellex Computing

Vellex Computing is a venture-backed startup developing next-generation hardware to accelerate artificial intelligence and high-performance computing. Spun off from Stanford University and backed by the U.S. Department of Energy and National Science Foundation, we are building a new class of processor designed to overcome the power and latency bottlenecks of traditional digital chips. Our technology enables orders-of-magnitude efficiency gains for critical applications in edge AI, robotics, and industrial optimization.

The Role

We are looking for a hands-on Engineering Manager to lead our analog design efforts in India. You will be one of our primary designers, spending a portion of your time designing, simulating, and verifying critical analog blocks. Simultaneously, you will lead a team of engineers, conduct design reviews, and manage project schedules. This is a unique opportunity to shape both the technical architecture and the engineering culture of a new design center from the ground up.

Your responsibilities will include:

• Hands-on Design: Design and implement high-performance analog/mixed-signal circuits (amplifiers, data converters, computational blocks) from concept to tape-out.
• Leadership: Mentor engineers, oversee layouts and simulations, and ensure design quality.
• Verification: Run and supervise extensive simulations (transient, AC, noise, Monte Carlo) to ensure robust performance across PVT.
• Strategy: Define block-level specifications and ensure seamless integration into the top-level system.

• Experience: 5+ years of hands-on experience in full-custom analog or mixed-signal IC design.
• Design Expertise: Proven track record of personally designing core blocks such as op-amps, bandgaps, LDOs, ADCs, or DACs.
• Leadership Potential: Ability to manage a small team and drive project timelines while remaining a heavy individual contributor.
• Education: MS or PhD in Electrical Engineering or a related field.
• Deep Submicron Knowledge: Solid understanding of CMOS device physics, layout effects, and challenges in advanced nodes.
• Tool Proficiency:  Proficiency with Synopsys EDA tools (e.g., Custom Compiler, HSPICE, PrimeSim) and physical layout flows.
• Full Cycle: Experience with at least one full tape-out cycle.

• Compensation: Competitive salary and equity package.
• Flexible Work: Hybrid model based in Delhi with flexible hours to accommodate international collaboration.
• First Principles Thinking: We love physics. We believe that by breaking problems down to their fundamental truths, even the most complex challenges can be solved.
• Share and Support: Our culture is collaborative. We are all about supporting each other through the ups and downs of startup life.
• Adapt and Excel: Agility is part of our DNA. We view mistakes as learning opportunities.

Vellex Computing is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. If you need assistance or accommodation during the application process, please let us know. Even if you don't meet every requirement, if you see yourself contributing to our team, we encourage you to apply!