FCT Engineer

• Perform full-chip timing analysis from early investigation through final implementation and tape-out.
  
• Perform static timing analysis and timing closure across multiple functional and test modes and corners.
  
• Develop, validate, and maintain timing constraints (SDC) for block and full-chip designs.
  
• Analyze timing scenarios and define appropriate margin strategies in collaboration with Synthesis and Design teams.
  
• Partner with Physical Design teams to debug timing violations and close designs through PnR and ECO cycles.
  
• Support timing signoff using industry-standard STA tools such as PrimeTime, Tempus, or equivalent.
  
• Analyze setup/hold violations, clock paths, crosstalk, OCV/AOCV/POCV, and signal integrity issues.
  
• Work closely with RTL, Physical Design, DFT, Synthesis, and other cross-functional teams to achieve timing closure.
  
• Support development and implementation of timing methodologies and signoff flows.
  
• Prepare timing reports, signoff documentation, and summaries to support project milestones and tape-out.
  

Requirements