Formal Verification CAD Engineer

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. Strong understanding of Digital Logic Design and Computer Architecture. Proficiency in HDLs (Verilog or SystemVerilog). Familiarity with functional verification concepts (simulation, testbenches, assertions). Basic scripting skills in Python, Perl, or Tcl. Coursework or project experience specifically in Formal Verification or Static Analysis. Knowledge of SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Exposure to industry-standard formal tools (e.g., Cadence JasperGold, Synopsys VC Formal, or Mentor Questasim Formal). Understanding of standard on-chip bus protocols (AMBA, AXI, APB) or memory consistency models. Experience with Linux/Unix environments and version control systems (Git, Perforce). Strong analytical and problem-solving skills. Ability to communicate technical details clearly to cross-functional teams. Eagerness to learn new tools and verification methodologies. Formal Property Verification (FPV): Develop and implement formal test plans to verify design blocks using SystemVerilog Assertions (SVA). Assertion Generation: Write properties (assertions, assumptions, and covers) to verify design specifications, architectural protocols, and standard interfaces (e.g., AXI, AHB). Debugging: Analyze formal proofs and counter-examples to root-cause design bugs; collaborate with RTL designers to fix issues. Specialized Checks: Perform focused formal apps checks, including Register Verification (FRV), Connectivity Checking, and deadlock/livelock detection. Automation: Develop scripts (Python, Tcl, Shell) to automate formal verification flows and regression environments. Coverage Analysis: Analyze formal coverage to ensure verification completeness and identify gaps in the design specification.