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GPU Physical Design Engineer (Lead/Staff/Sr Staff)

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Job Description - GPU Physical Design Engineer (Lead/Staff/Sr Staff)

## \nCompany:\n\nQualcomm India Private Limited\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e Hardware Engineering\n\nGeneral Summary:\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what\u0027s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. \nOR \nMaster\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. \nOR \nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\n## Role Overview\n\nAs a Lead / Staff / Senior Staff Physical Design Engineer in the GPU team, you will be responsible for the end\u2011to\u2011end physical implementation of high\u2011performance, low\u2011power GPU cores used across mobile, compute, and automotive platforms. You will work closely with RTL, micro\u2011architecture, DFT, STA, and signoff teams to deliver best\u2011in\u2011class PPA (Performance, Power, Area) on advanced technology nodes.\n\nStaff and Senior Staff engineers are expected to drive block\u2011level ownership, make critical PPA trade\u2011offs, mentor junior engineers, and influence physical design methodology, while Lead engineers focus on strong technical execution and convergence.\n\n## \n\n## Key Responsibilities\n\n * Own complete Physical Design / Physical Implementation flow for complex GPU cores, including:\n\n * Floorplanning\n\n * Place and Route\n\n * Clock Tree Synthesis (CTS)\n\n * Static Timing Analysis (STA)\n\n * Physical Verification (DRC/LVS)\n\n * Formal verification\n\n * Power Delivery Network (PDN) design\n\n * Drive timing closure for high\u2011frequency, data\u2011path\u2011intensive GPU blocks across multi\u2011mode, multi\u2011corner scenarios\n\n * Optimize PPA trade\u2011offs and push designs to aggressive performance and power targets on advanced technology nodes\n\n * Perform timing ECOs, functional ECO roll\u2011ins, and debug critical timing, power, and physical violations\n\n * Collaborate closely with RTL, micro\u2011architecture, DFT, and signoff teams to resolve constraints, clocking, and implementation issues\n\n * Develop and apply low\u2011power implementation techniques and customized P\u0026R strategies for GPU cores\n\n * Contribute to PD flow automation, methodology improvements, and efficiency enhancements using scripting\n\n * Mentor junior engineers and provide technical leadership (Staff / Senior Staff levels)\n\n\n\n\nRequired Technical Skills\n\n * 6 to 15 years of experience in Physical Design / Physical Implementation for complex SoCs or high\u2011performance cores (GPU or CPU preferred)\n\n * Strong hands\u2011on experience with industry\u2011standard P\u0026R tools such as Synopsys ICC2 and/or Cadence Innovus\n\n * Strong expertise in Static Timing Analysis using PrimeTime and/or Tempus\n\n * Deep understanding of advanced STA concepts and clocking architecture\n\n * Experience with multi\u2011corner timing closure and high\u2011frequency designs\n\n * Solid understanding of PDN design, power optimization, and leakage control\n\n * Proficiency in Tcl and/or Perl scripting for flow automation\n\n * Experience working on advanced deep sub\u2011micron technology nodes\n\n\n\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm\u0027s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.\n
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