Lead RTL Design Engineer

Regami Solutions is looking for a Lead RTL Engineer with deep expertise in RTL design and SoC development. This role focuses on the architecture, design, and delivery of high -quality RTL for complex IP, subsystem, and SoC -level designs, with strong emphasis on microprocessor architectures, interconnects, memory subsystems, and high -speed interfaces.

Requirements

Areas of Responsibility

• Contribute to RTL design and delivery
  across multiple IP, subsystem, and SoC -level projects.
  
• Work closely with system architects to
  define high -level specifications that are robust, scalable, and
  implementation -ready.
  
• Interface with verification and validation
  teams to ensure functional correctness, quality, and design robustness.
  
• Collaborate effectively with
  cross -functional R&D teams including Verification, Digital IP, Design
  Enablement, Emulation, Validation, and Software to achieve project milestones.
  
• Drive continuous improvement in design
  methodologies and best practices to achieve Zero -Defect silicon
  outcomes.
  
• Engage with Subject Matter Experts (SMEs)
  and technical leaders across architecture, systems, emulation, SoC design,
  software, physical design, and IP teams to influence technical direction and
  build strong engineering networks
  

Qualifications

• Bachelor’s or Master’s degree in Electrical
  Engineering, Computer Science, or a related discipline.
  
• 7+ years of hands -on experience in IP /
  Subsystem RTL Design; minimum 5+ years of relevant domain experience.
  
• Strong experience in testbench design and
  development using UVM methodology for IP, subsystem, and SoC verification.
  
• Solid understanding of microcontroller and
  microprocessor architectures, interconnects, and cache coherency mechanisms.
  
• Experience with industry -standard protocols
  such as AHB, AXI, CHI, and memory technologies including ROM, RAM, Flash,
  LPDDR, DDR3/DDR4, and memory controllers.
  
• Proficiency in Verilog, SystemVerilog,
  C/C++, and Shell scripting.
  
• Working knowledge of scripting languages
  such as Perl, TCL, or Python is an added advantage.
  
• Strong grasp of metric -driven verification,
  including functional and code coverage.
  
• Expertise in directed and
  constrained -random verification methodologies.
  
• Good understanding of formal verification
  techniques and assertion -based verification.
  
• Experience debugging designs pre - and
  post -silicon, both in simulation environments and on hardware benches.
  
• Hands -on experience with SystemVerilog
  front -end tools including simulators, waveform viewers, lint, CDC, RDC, and
  related FE methodologies.
  
• Strong domain knowledge in clocking
  architectures, power management, system modes, debug, and security
  architectures.
  
• Excellent written and verbal communication
  skills.
  

Additional Plus Skills

• Experience with high -speed peripherals such
  as DDR, PCIe, Ethernet.
  
• Exposure to GPU, VPU (Video Processing
  Units), NICs, FlexNOC interconnects.
  
• Experience with Flash memory subsystems.