NoC(Network-on-chip) deployment architect

## \nCompany:\n\nQualcomm India Private Limited\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e Hardware Engineering\n\nGeneral Summary:\n\nThe QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics. \n\nTo this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions. \n\nYou will join the solutions deployment team with the mission of deploying and supporting the QITC NoC technology across all the SoCs of Qualcomm portfolio (Mobile, Automotive, Servers, IoT, Connectivity, etc..). \n\nThis is a challenging position, working on most innovative technologies, surrounded by experts but also by users of our technology all over the world and from various teams (SoC Architecture, HW and SW Design, Verification, Debug, Post Silicon). \n\nResponsibilities\n\n * Responsibility of Architecture and Design for Next-gen Qualcomm coherent and non-coherent interconnect fabric\n * Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, software, verification, emulation, ...) to ensure our technology is used efficiently in Qualcomm SoCs \n * Contribute to the definition of interconnect requirements and configuration in the various SoCs \n * Be responsible for the technical support of new QITC solutions \n * Help resolving NoC micro-architecture and NoC integration issues \n * Participate in defining new solutions and improvements for our technology \n * Develop in-depth technical material and organize trainings for different teams worldwide \n\n\n\nSkills/Experience\n\n * Strong understanding of overall SoC development flow: SoC architecture, RTL design and verification, SoC performance and DDR memory channel, physical implementation, silicon debug. \n * Good knowledge in system level features such as memory-mapping, MMUs, Quality of service, cache infrastructure, security schemes, etc.. \n * Strong analytical skills for debug in simulation, emulation or silicon bring-up environments. \n * Understand of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI/NoC concepts. \n * Working knowledge of Lint, CDC, PLDRC, CLP etc\n * Python \u0026 Perl scripting \n * Ability to quickly react and adapt to changes. \n * Excellent communication skills. \n\n\n\nMinimum Qualifications\n\n * Master\u2019s degree in Microelectronics, Computer Science, or related field. \n * Preferably 8-12 years of solid experience in design, architecture and/or application engineering in SoC/ASIC development cycle. \n * Standard SoC knowledge: Multimedia Ips, GPU, multi-core CPU architecture, Processors, Caches, memory controller, interconnects, ... and related design, integration and verification challenges \n\n\n\nPreferred Qualifications\n\nOne or multiple qualifications in the below list would be a great advantage: \n\n * Understanding of on-chip protocols like CHI/AHB/AXI/ACE/ACE-Lite\n * SoC high speed protocols and chiplet architectures \n * Coherency protocols \n\n\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. \nOR \nMaster\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. \nOR \nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. 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