Principal DFT Engineer (Design for Test)

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

As an Astera Labs’ Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Basic qualifications:

• Minimum of bachelor’s degree in computer engineering/ electrical engineering, Masters preferred.


• Minimum 12+ years of experience in a semiconductor company as a DFT engineer


• Must be local or willing to relocate

Required experience:

• Chip design, Verilog and System Verilog


• Verification, UVM methodology


• ATPG tools


• Scan insertion tools


• Gate-level simulations


• Static timing analysis


• Scripting (Perl/Tcl)


• Familiarity with ATE


• Hands-on expertise with commercial test generation tools for large complex designs


• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression


• Experience running test compression software


• Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools

Preferred experience:

• Experience with defining and implementing SOC level verification on large designs.


• Working with 93k Tester


• Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.