Principal Engineer, ASIC Validation

Req. ID:\n\nJR96931 Principal Engineer, ASIC Validation\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nJob responsibilities At Glance:\n\n * Overall ownership of PCIe/LPDDR validation in Architecture, Pre-Silicon, Board Design, Post-Silicon activities, Proficiency in Debug Skills \u0026 Interoperability\n\n * Interact with Architecture/Design/FW teams to identify actual FW implementation and plan/perform validation accordingly\n\n * Review SoC Verification plan for PCIe/LPDDR sub system and Create/understand PCIe/LPDDR Validation plan with SOC C, AE, FW teams and architect/review/update C/FW based tests\n\n * Develop understanding on SoC and perform Processor based SoC verification and Emulation using C/FW/AE Flow\n\n * Should be able to run SOC C based simulations for test case understanding and debug using VCS\n\n * Involve in Silicon Bring-up activity and support FW bring-up\n\n * Work with overseas teams for PCIe/LPDDR bring-up/debug\n\n\n\n\nJob Qualifications\n\n * Bachelors/Masters or equivalent experience in Engineering\n\n * Detailed Knowledge of PCIe/LPDDR Standards is must. PCIe G5/G6 or LPDDR5 would be preferred.\n\n * Experience with high\u2011speed serial protocols and SerDes PHY behavior\n\n * Good understanding on PCIe / NVME Architecture or LPDDR architecture\n\n * Minimum 14+ years of Processor based SoC, and hands-on PCIe validation experience with C/FW tests\n\n * Hands on LA, PCIe Switches, PA, Exerciser set up (Viavi*, Lecroy), Hardware set up, Debug set up is A Must\n\n * Good To Have - Knowledge of industry standard interfaces, such as ONFI, AXI is an advantage\n\n * Good To Have - Debug, bring up experience with SNPS PCIe Controller, PHY is an advantage\n\n * Proven experience in scripting languages such as Python / Perl / TCL\n\n * Good written and oral communication\n\n * Excellent Great Teammate, Positive attitude, well-mannered mature behavior is must\n\n\n\n\nJob Profile(s):\n\nASIC Engineer 5\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n