RISC V CPU Design Verification Sr Lead Engineer

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Strong understanding of power management features in CPUs and CPU based Socs. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Develop and execute verification plans for units and features of a CPU design Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators. Work closely with system architects, design team, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. BE/BTech degree in CS/EE with 6+ years' experience (A MUST). Implementation of assembly and C language tests for verifying CPU architecture. Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.