RTL Design (Peripherals) -Staff

Experienced in RTL design using Verilog / System Verilog. Experienced in Linting, CDC , LEC and preferably Low Power check tools. Experienced in database management flows with Clearcase/Clearquest. Knowledge of RTL and Gate-Level power analysis. Knowledge and experience of defining HW/FW interfaces. Knowledge of low power design techniques Ability to program effectively in Verilog, C/C++, Python, Perl Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skill Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.