Senior Design Verification Engineer

This role is for one of the Weekday's clients

Min Experience: 6 years

Location: Bangalore, Hyderabad

JobType: full-time

We are seeking an experienced Senior Design Verification Engineer to contribute to the development and verification of advanced semiconductor designs built on 7nm and 5nm process technologies. This role focuses on verifying domain-specific processors designed for high-performance computing, networking, and cloud infrastructure environments.

The position involves working on processors used in IaaS and smart-switch applications, leveraging programmable architectures to deliver software-defined capabilities with hardware-level performance. The engineer will collaborate closely with architecture and design teams to ensure functional correctness, performance reliability, and silicon readiness across the entire chip lifecycle.

Key Responsibilities

Verification Planning & Strategy

• Define comprehensive verification strategies, methodologies, and test plans.
• Develop and execute verification plans at Unit, IP, Subsystem, and SoC levels.

Testbench Development

• Design and implement SystemVerilog-based test benches including stimulus generation, checkers, assertions, and coverage models.
• Develop verification components such as transactors, BFMs (Bus Functional Models), and coverage points.

Functional & Performance Validation

• Identify and debug issues related to architecture, functionality, and performance.
• Perform detailed analysis to isolate and resolve design bugs efficiently.

Verification Infrastructure

• Contribute to the development and enhancement of verification methodologies and reusable infrastructure.
• Ensure scalability and maintainability of verification environments.

Full Lifecycle Verification Support

• Support verification across multiple stages including module-level testing, full-chip verification, emulation, prototyping, silicon bring-up, and manufacturing diagnostics.
• Assist in validating compiler interactions and platform-level software integration.

Cross-Team Collaboration

• Work closely with micro-architecture and hardware design teams to ensure alignment on design intent and verification coverage.

Required Skills & Experience

• Strong understanding of computer architecture and digital design fundamentals.
• Hands-on experience with SystemVerilog and Universal Verification Methodology (UVM).
• Proficiency in C/C++ programming for verification environments.
• Experience developing and executing verification plans at Unit, IP, Subsystem, and SoC levels.
• Strong expertise in SystemVerilog testbench development, including stimulus generation, assertions, checkers, and coverage modeling.
• Experience with industry-standard simulation tools such as VCS or equivalent.
• Familiarity with debugging tools such as Debussy or DVE.
• Excellent debugging, analytical, and problem-solving skills.

Key Skills

• SystemVerilog
• Universal Verification Methodology (UVM)
• SoC Verification
• AMBA Protocols
• Computer Architecture
• Networking Systems
• Digital Design Verification
• Simulation & Debugging Tools